2007-2008 AbstractsComputer Science Distinguished Lecturer Series:Log-Based Transactional MemoryMark D. Hill, The University of Wisconsin-Madison
4:10 p.m., Monday, October 1, 2007 Open Reception: 3:30 p.m. (Rm 301 HRBB) AbstractFor decades, computer architects have turned the increasing transistor bounty provided by MOORE'S LAW into ever-doubling single-threaded performance. As such efforts recently stalled, architects turned to using the continued transistor bounty to support more CORES per chip: DUAL CORE, QUAD CORE, ..., MULTICORE. Computer users will value (and buy) multicore chips only if they get increased performance. This requires that programmers be able to author effective parallel programs, which heretofore has been robustly done in only a few domains. We advocate that architects spend some transistors to make parallel programming easier. Transactional memory may be one way to do this. TRANSACTIONAL MEMORY (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. HARDWARE TM implementations leverage caches and coherence to be fast. We illustrate TM's potential with LOG-BASED TRANSACTIONAL MEMORY SIGNATURE EDITION (LogTM-SE) that implements TM in software visible structures—logs and signatures—that allow fast operation in the common case and correct operation when transactions exceed hardware resources. BiographyMARK D. HILL (www.cs.wisc.edu/~markhill) is a professor in the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin-Madison, where he also co-leads the Wisconsin Multifacet Project (www.cs.wisc.edu/multifacet) with David Wood. His research interests include parallel computer system design, memory system design, and computer simulation. He earned a PhD from the University of California, Berkeley. He is an ACM Fellow and a Fellow of the IEEE. Faculty Contact: Lawrence Rauchwerger (rwerger [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:Developments in Holographic AlgorithmsDr. Jin-Yi Cai, The University of Wisconsin-Madison
4:10 p.m., Monday, November 5, 2007 Open Reception: immediately following Dr. Cai's presentation AbstractComputational Complexity Theory is the study of intrinsic difficulties of computational problems. The most prominent open problem is the conjecture that P is not equal to NP. In essence this conjecture states that it is intrinsically harder to find proofs than to verify them. It has a fundamental importance in many areas of computer science, from computer security to our basic understanding of the nature of efficient computation. Valiant's new theory of holographic algorithms is one of the most beautiful ideas in algorithm design in recent memory. It represents a totally original attack on the P and NP question. Alternatively it can be seen as a novel approach to study constrained satisfiability problem. In this theory, information is represented by a superposition of linear vectors in a holographic mix. This mixture creates the possibility for exponential sized cancellations of fragments of local computations. The underlying computation is done by invoking the Fisher-Kasteleyn-Temperley method for counting perfect matchings for planar graphs, which uses Pfaffians and runs in polynomial time. In this way some seemingly exponential time computations can be done in polynomial time, and some minor variations of the problems are known to be NP-hard or #P-hard. Holographic algorithms challenge our conception of what polynomial time computations can do, in view of the P vs. NP question. In this talk we will survey the developments in holographic algorithms. No specialized background is assumed. BiographyJin-Yi Cai received his Ph. D. in Computer Science from Cornell University in 1986. He held faculty positions at Yale University (1986-1989), Princeton University (1989-1993), and SUNY Buffalo(1993-2000), rising from Assistant Professor to Professor. He is currently a Professor of Computer Science at the University of Wisconsin--Madison. He received a PYI award, a Sloan Fellowship, a Guggenheim Fellowship, and a Morningside Silver Medal of Mathematics. He also received a Humboldt Research Award for Senior U.S. Scientists, and has been elected a Fellow of ACM. He research area is primarily computational complexity theory. He has written and published over 100 research papers. His recent paper with Pinyan Lu on holographic algorithms won the best paper award at ICALP 2007. This year he is a Radcliffe Fellow at Harvard University. Faculty Contact: Jianer Chen (chen [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:Supporting U.S. Innovation and Prosperity in the 21st CenturyDr. William A. Wulf, University of Virginia
4:10 p.m., Wednesday, November 28, 2007 Open Reception: immediately following Dr. Wulf's presentation AbstractIn 2005 Congress asked the Academies "What does the U.S. need to do to prosper in the 21st Century?" The Academies response was a report entitled Rising Above the Gathering Storm. Together with Tom Freidman's book and about a dozen reports from the likes of the Council on Competitiveness and the National Association of Manufacturers, this report identified innovation as a prime competitive strength of the U.S. and recommended ways to enhance that strength. After quickly reviewing the situation laid out in these reports, this talk will go on point out a number of other areas where the laws, policies, regulations and institutions that support innovation need to be rethought in terms of how they do (or don't) match the needs of future technologies. BiographyWilliam A. Wulf is the AT&T Professor of Computer Science at the University of Virginia. He received the first Computer Science Ph.D. ever awarded at the University of Virginia in 1968. He then joined Carnegie-Mellon University as Assistant Professor of Computer Science, becoming Associate Professor in 1973 and Professor in 1975. In 1981 he left Carnegie-Mellon and founded Tartan Laboratories and served as Chairman and Chief Executive Officer until 1988. In 1988-1990 he was Assistant Director of the National Science Foundation. In 1990 he returned to the University of Virginia as AT&T Professor and University Professor. Dr. Wulf is a Fellow of the National Academy of Engineering, a Fellow of ACM, a Fellow of the IEEE, and a member of the American Academy of Arts and Sciences. In 1997 he was elected President of the National Academy of Engineering, which operates under a congressional charter and presidential executive orders that call on it to provide advice to the government on issues of science and engineering. He has directed over 25 Ph.D. theses and is the author or co-author of three books, two patents and over 100 papers. Professor Wulf's research interests revolve around the hardware/software interface, and thus span programming systems and computer architecture. He designed Bliss, a systems-implementation language adopted by DEC, and was one of the architects of the DEC PDP-11, a highly successful minicomputer. He designed and constructed the C.mmp multiprocessor, and Hydra, one of the first operating systems to explore capability-based protection. He developed PQCC, a technology for the automatic construction of optimizing compilers, and designed the WM pipelined processor. Dr. Wulf also investigated the design of scalable high performance memory systems, computer security, and hardware-software co-design. Faculty Contact: Valerie E. Taylor (taylor [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:Assistive Technology for the Aesthetically ImpairedDr. John C. Hart, University of Illinois at Urbana-Champaign
4:10 p.m., Monday, February 18, 2008 Open Reception: immediately following Dr. Hart's presentation AbstractModern computing increasingly enables personal expression with consumer-level digital content creation (DCC) software. Feature-laden DCC authoring applications provide powerful tools for creating text, images, audio and video, but very little guidance to an untrained consumer user base for writing compelling stories, taking good photographs, composing beautiful music, or editing engaging videos. We scratch the surface of this problem by considering how users, largely untrained in illustration, visually communicate their ideas by copying professional drawings from clip-art collections. We describe two recent solutions that render 3-D models automatically as custom stylized illustrations. BiographyJohn C. Hart is a Professor in the Department of Computer Science at the University of Illinois, Urbana-Champaign, where he studies computer graphics and computational topology. He is the Editor-in-Chief of ACM Transactions on Graphics, a co-author of "Real-Time Shading," a contributing author for "Texturing and Modeling: A Procedural Approach" and an executive producer of the documentary "The Story of Computer Graphics." He received his B.S. from Aurora University in 1987, and a Ph.D. in 1991 from the Electronic Visualization Laboratory at the University of Illinois at Chicago. His work is currently supported by Adobe, Intel, Microsoft, NAVTEQ, NVIDIA and the NSF. Faculty Contact: Scott Schaefer (schaefer [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:If You Knew Where All the Bugs Were ...Elaine Weyuker, AT&T Labs, Florham Park, NJ
4:10 p.m., Wednesday, February 27, 2008 Open Reception: immediately following Dr. Weyuker's presentation AbstractIt would obviously be very valuable to know in advance which files in the next release of a large software system are most likely to contain the largest numbers of faults. To accomplish this, we developed a negative binomial regression model and used it to predict the expected number of faults in each file of the next release of a system. The predictions are based on code characteristics and fault and modification history data. We will discuss what we have learned from applying the model to three large industrial systems, each with multiple years of field exposure, and tell you about our success in making accurate predictions and some of the lessons learned and issues that had to be dealt with. BiographyElaine Weyuker is an AT&T Fellow doing software engineering research at AT&T Labs. Prior to moving to AT&T she was a professor of computer science at NYU's Courant Institute of Mathematical Sciences. Her research interests currently focus on software fault prediction, software testing, and software metrics and measurement. In an earlier life, Elaine did research in Theory of Computation and is the co-author of a book "Computability, Complexity, and Languages" with Martin Davis and Ron Sigal. Elaine is the recipient of the 2007 ACM/SIGSOFT Outstanding Research Award. She is also a member of the US National Academy of Engineering, an IEEE Fellow, and an ACM Fellow and has received IEEE's Harlan Mills Award for outstanding software engineering research, Rutgers University 50th Anniversary Outstanding Alumni Award, and the AT&T Chairman's Diversity Award as well has having been named a Woman of Achievement by the YWCA. She is the chair of ACM's Committee on Women in Computing (ACM-W) and a member of the Executive Committee of the Coalition to Diversify Computing. Faculty Contact: Valerie E. Taylor (taylor [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:TM and the Art of Parallel ProgrammingDr. Siddhartha Chatterjee, IBM Austin Research Laboratory, Austin, TX
4:10 p.m., Wednesday, March 19, 2008 Open Reception: immediately following Dr. Chatterjee's presentation AbstractTransactional Memory (TM) has been hailed as a key to cracking the parallel programming problem for the multicore era. Through a workload-driven study, we scrutinize the benefits that TM can bring in terms of performance and productivity. We also compare the performance of several STM implementations and examine the opportunities for compiler and runtime optimizations in this context. BiographyDr. Siddhartha Chatterjee is the Director of the Austin Research Laboratory (ARL), one of IBM's eight worldwide research laboratories. He also serves as the Research area strategist for systems architecture. He has held various technical, managerial, strategy, and staff positions during his time at the IBM Research Division. Most recently, he was senior manager of the Systems Solutions and Architecture group at IBM Thomas J. Watson Research Center, Yorktown Heights, NY. Earlier, he was the leader of the Blue Gene performance team. Dr. Chatterjee received his B.Tech. in electronics and electrical communications engineering in 1985 from the Indian Institute of Technology, Kharagpur, and his Ph.D. in computer science in 1991 from Carnegie Mellon University. Before joining IBM Research, he was a visiting scientist at the Research Institute for Advanced Computer Science (RIACS) in Mountain View, California, from 1991 through 1994, and was assistant and associate professor of computer science at the University of North Carolina at Chapel Hill from 1994 through 2001. Dr. Chatterjee has performed research and published in the areas of compilers for parallel languages, computer architecture, and parallel algorithms. His research interests include the design and implementation of programming languages and systems for high-performance applications, memory hierarchy issues in high-performance systems, and software quality. He is a member of ACM and Sigma Xi, and a senior member of IEEE. Faculty Contact: Valerie E. Taylor (taylor [at] cs.tamu.edu) Computer Science Distinguished Lecturer Series:Multiprocessor Architectures for Speculative MultithreadingDr. Josep Torrellas, University of Illinois, Urbana-Champaign
28 Mon. 4:10pm (Rm 124 HRBB) Open Reception: immediately following Dr. Torrellas' presentation AbstractOne of the biggest challenges facing computer architecture today is the design of parallel architectures that make it easy for programmers to write parallel codes. One of the architectural technologies that is showing great versatility and potential in this direction is Speculative Multithreading. In this talk, I will discuss the many uses of this technology in multiprocessors, and its remarkable potential for performance and programmability (Thread-Level Speculation, Speculative Synchronization, Transactional Memory, and BulkSC), hardware reliability (Paceline), and software dependability (ReEnact and Iwatcher). BiographyJosep Torrellas is a Professor and Willett Faculty Scholar at the University of Illinois. Prior to being at Illinois, Torrellas received a PhD from Stanford University. He also spent a year IBM's T.J. Watson Research Center. Torrellas's research area is multiprocessor computer architecture. He has been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects, and lead the Illinois Aggressive COMA and FlexRAM Intelligent Memory projects. He is a member of ACM and Sigma Xi, and a senior member of IEEE. Faculty Contact: Lawrence Rauchwerger (rwerger [at] cs.tamu.edu) |
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