DUNCAN M. "HANK" WALKER

Professor and Graduate Advisor

Email: walker@cs.tamu.edu
Phone: 979-862-4387
Office: HRBB 515B
http://faculty.cs.tamu.edu/walker

Ph.D., Computer Science, Carnegie Mellon University, 1986
M.S., Computer Science, Carnegie Mellon University, 1984
B.S., Engineering (Honors), California Institute of Technology, 1979

RESEARCH INTERESTS

Integrated circuit test, defect-based test, delay test, IDDQ test, fault diagnosis, realistic fault modeling, parametric and functional yield prediction

SELECTED RESEARCH SUPPORT

"Reliability Screening via Outlier Analysis," National Science Foundation, 9/2003 to 8/2006.

"Delay Fault Modeling, Test and Diagnosis," National Science Foundation, 9/2001 to 8/2005.

AWARDS

E. D. Brockett Professorship, 2007-2008

Lockheed Martin Aeronautics Company Excellence in Engineering Teaching Award, 2006

Dwight Look College of Engineering Fellow, Texas A&M, 2006-2007

AMD Fellow, College of Engineering, Texas A&M, 2002-2003

TEES Fellow, College of Engineering, Texas A&M, 1998-1999

EXPERIENCE

Professor, Department of Computer Science, Texas A&M University, 2006 - present

Associate Professor, Department of Computer Science, Texas A&M University, 1993-2006

Associate Head, Department of Computer Science, Texas A&M University, 2000-2003

Visiting Scholar, IBM Austin Research Laboratory, 1997

Assistant Director and Research Engineer, SRC-CMU Research Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie Mellon University, 1986-1993

Teaching Assistant, California Institute of Technology, 1978-1979

Part Time Engineer, Digital Equipment Corp., Hudson, Massachusetts, 1979-1981

Engineer, Hughes Aircraft Co., Culver City, California, 1977, 1978

PROFESSIONAL ACTIVITIES AND SERVICE

Vice-General Chair, IEEE International Workshop on Defect Based Testing, Santa Clara, CA, October 2006.

Steering Committee, IEEE International Workshop on Defect Based Testing, 2005-present.

Program Committee, IEEE International Conference on Computer-Aided Design.

Chair 2003, Vice Chair 2002, Program Chair 2001, IEEE International Workshop on Defect Based Testing.

Finance Chair, IEEE International Workshop on Memory Technology, Design, and Testing, 1997, 1998.

Editorial Board, IEEE Transactions on Computers, 1992-1997.

General Chair 1992, Program Chair 1991, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Member, Yield Enhancement Cross-Cut Technology Working Group, Semiconductor Industries Association (SIA) International Technology Roadmap for Semiconductors.

SELECTED PUBLICATIONS

H. S. Kim and D. M. H. Walker, "Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits," IEEE International Workshop on Microprocessor Test and Verification (MTV), Austin TX, November 2006.

B. Xue and D. M. H. Walker, "Is IDDQ Test of Microprocessors Feasible?" IEEE International Workshop on Microprocessor Test and Verification (MTV), Austin TX, November 2005.

L. Wu and D. M. H. Walker, "A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, pp. 178-186, Oct. 2005.

B. Xue and D. M. H. Walker, "IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop," IEEE International Test Conference, Austin, TX, paper 37.1, pp. 954-963, Oct. 2005.

J. Wang, Z. Yue, X. Lu, W. Qiu, W. Shi and D. M. H. Walker, "A Vector-based Approach for Power Supply Noise Analysis in Test Compaction," IEEE International Test Conference, Austin, TX, paper 22.2, pp. 517-526, Oct. 2005.