DUNCAN M. "HANK" WALKER

Professor and Graduate Advisor

Email: walker@cse.tamu.edu
Phone: 979-862-4387
Office: HRBB 515B
http://faculty.cse.tamu.edu/walker

Ph.D., Computer Science, Carnegie Mellon University, 1986
M.S., Computer Science, Carnegie Mellon University, 1984
B.S., Engineering (Honors), California Institute of Technology, 1979

RESEARCH INTERESTS

Integrated circuit test, defect-based test, delay test, IDDQ test, fault diagnosis, realistic fault modeling, parametric and functional yield prediction

SELECTED RESEARCH SUPPORT

"Delay Test and Diagnosis Considering DSM and Power," National Science Foundation, 2007 to 2010.

"At-Speed Tests Considering DSM and Power," Semiconductor Research Corporation, 2007 to 2010.

AWARDS

E. D. Brockett Professorship, 2007-2008

Lockheed Martin Aeronautics Company Excellence in Engineering Teaching Award, 2006

Dwight Look College of Engineering Fellow, Texas A&M, 2006-2007

AMD Fellow, College of Engineering, Texas A&M, 2002-2003

TEES Fellow, College of Engineering, Texas A&M, 1998-1999

EXPERIENCE

Professor, Department of Computer Science and Engineering, Texas A&M University, 2006 - present

Associate Professor, Department of Computer Science, Texas A&M University, 1993-2006

Associate Head, Department of Computer Science, Texas A&M University, 2000-2003

Visiting Scholar, IBM Austin Research Laboratory, 1997

Assistant Director and Research Engineer, SRC-CMU Research Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie Mellon University, 1986-1993

Teaching Assistant, California Institute of Technology, 1978-1979

Part Time Engineer, Digital Equipment Corp., Hudson, Massachusetts, 1979-1981

Engineer, Hughes Aircraft Co., Culver City, California, 1977, 1978

PROFESSIONAL ACTIVITIES AND SERVICE

Vice-General Chair, IEEE International Workshop on Defect Based Testing, Santa Clara, CA, October 2006.

Steering Committee, IEEE International Workshop on Defect Based Testing, 2005-present.

Program Committee, IEEE International Conference on Computer-Aided Design.

Chair 2003, Vice Chair 2002, Program Chair 2001, IEEE International Workshop on Defect Based Testing.

Finance Chair, IEEE International Workshop on Memory Technology, Design, and Testing, 1997, 1998.

Editorial Board, IEEE Transactions on Computers, 1992-1997.

General Chair 1992, Program Chair 1991, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Member, Yield Enhancement Cross-Cut Technology Working Group, Semiconductor Industries Association (SIA) International Technology Roadmap for Semiconductors.

SELECTED PUBLICATIONS

Z. Wang and D. M. H. Walker, “Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric,” IEEE VLSI Test Symposium, Santa Cruz, CA, May 2009.

Z. Wang and D. M. H. Walker, “Dynamic Compaction for High Quality Delay Test,” IEEE VLSI Test Symposium, Rancho Bernardo, CA, May 2008, paper 8.1.

S. Sabade and D. M. H. Walker, “Estimation of Fault-Free Leakage Using Wafer-Level Spatial Information,” IEEE Transactions on VLSI Systems, vol. 14, no. 1, January 2006, pp. 91-94.

X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “Longest Path Selection for Delay Test under Process Variation,” IEEE Transactions on Computer-Aided Design, vol. 24, no. 12, December 2005, pp. 1924-1929